MOS pull-up or pull-down logic circuit having equalized discharge time delays and layout avoiding crossovers

摘要

A MOS logic circuit comprises two P channel MOSFETs connected in parallel between a positive power source VDD and a logic signal output terminal and two series circuits connected in parallel between a ground voltage source VSS and the terminal, each series circuit being comprised of serially connected two N channel MOSFETs. The gate electrodes of the MOSFETs located in the corresponding positions in the respective series circuits are connected to first and second logic signal input terminals, respectively. Similarly, the gate electrodes of the other MOSFETs located in the corresponding positions in the respective series circuits are connected to the second and first logic signal input terminals, respectively.