| 摘要 |
PURPOSE:To expand a logical and a physical address space and to improve the throughput in program manipulation by widening the width of an entry into a TLB (address conversion buffer). CONSTITUTION:The high-order address of a logical address sent out of a central processor 1 for the 1st time is latched by a logical address latch 3 and a physical address stored at the low-order part of the TLB 2 equipped with an extension area is read out on the basis of the latched address and latched by a physical address latch 4. Then, while the high-order part of the TLB 2 is read out, the low-order address of the 2nd logical address from the central processor 1, i.e. an address in a physical address is sent out, so a physical address is composed of the low-order address of said logical address, the physical page address which is already latched, and the physical page address contained in the high-order part of the TLB 2 to access a main storage MS.
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