| 摘要 |
PURPOSE:To surely ignite all thyristors by keeping a gate pulse to supply till a time T3 succeedingly if not all thyristors are ignited by a gate pulse of width T1. CONSTITUTION:If not all thyristors are ignited even with an elapsed time TD after the application of a gate pulse P, since the output of an AND circuit 10 is not lost, the level of an output of an ON-DELAY circuit 12 goes to '1' after the time TD. The output of the AND circuit 14 goes to '1' when the output of the usle generating circuit 11 goes to '0', and a pulse generating circuit 15 generates a pulse signal of width T3 just after the time T1. When all the thyristors are ignited within the time T3, the output of the AND circuit 10 and the ON-DELAY circuit 12 goes to '0' at that point of time. Thus, a gate pulse P having a pulse width (T1+T3) is outputted from the OR circuit 16.
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