发明名称 INSPECTING METHOD FOR SEMICONDUCTOR DEVICE
摘要 PURPOSE:To reduce the influence of movable ions upon the surface of silicon by; applying a voltage higher than the reverse dielectric strength of junction for a short time between junction electrodes of a planar type transistor (TR) which has a protection insulating film on the surface or a diode, and then conducting a normal test of the reverse dielectric strength. CONSTITUTION:Phosphor is diffused in a p-type silicon substrate 1 to form a base area 2, boron is diffused to form an emitter area 3, and then an emitter electrode 4, a base electrode 5, and a collector electrode 6 are formed. The TR manufactured as mentioned above is applied with a reverse bias voltage higher than the dielectric strength that an element has between the electrodes 6 and 5 in a wafer state. At this time, a current flows and the current value is suppressed within a range wherein the element does not break down. Namely, a capacitor 8 is charged and then discharged to allow the current to flow between the collector and base momentarily. Consequently, movable ions move to an area where the element is not affected and the influence upon the surface of the element is reduced, thereby suppressing variation in dielectric strength and deterioration.
申请公布号 JPS62297762(A) 申请公布日期 1987.12.24
申请号 JP19860140849 申请日期 1986.06.17
申请人 MATSUSHITA ELECTRONICS CORP 发明人 KAWASAKI HIDEO;ADACHI MASAMICHI;IHARA MASAHIRO;YAMAZAKI AKIRA
分类号 G01R31/26;H01L21/66 主分类号 G01R31/26
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