| 摘要 |
During the receipt of a result of comparison from the phase detector representing that the synchronization signal is phase-delayed behind the input signal, the selection circuit sequentially selects the M number of counters, one by one, in a cyclic fashion, in such a direction as to permit the reference clock input to be phase-advanced correspondingly, so that the frequency-divided output signal from the counter to the phase detector can be sequentially phase advanced by 1/M of one cycle of the reference clock. During the receipt of a result of the comparison indicating that the synchronization signal is phase-advanced ahead of the input signal, on the other hand, the selection circuit sequentially selects the M number of counters, one by one, in a cyclic fashion, in such a direction as to allow the reference clock input to be phase-delayed, so that the frequency divided output signal from the counter to the phase detector can be sequentially phase-delayed by 1/M of one cycle of the reference click. When a phase difference occurs between the input signal and the synchronization signal, one cycle time of the synchronization signal is increased or decreased by 1/M of one cycle of the reference clock, thus assuring an enhanced time resolution.
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