| 摘要 |
PURPOSE:To obtain a memory device having high integration density, by forming gate electrodes and a word line with a first conductor layer in a multilayer interconnection structure, forming a grounding line with a second conductor layer comprising a high-melting-point material, and forming resistor elements with a third conductor layer. CONSTITUTION:On a semiconductor substrate 16, first-third conductor layers are formed and a multilayer interconnection substrate is obtained. Gate electrode 11a-14a of MOS transistors 11-14 and a word line 17 are formed with said first conductor layer. Said second conductor layer is formed with high-melting- point metal or a compound including high-melting-point metal. A grounding line 41 is formed with said conductor layer. Resistor elements 27 and 28 are formed with said third conductor layer. The planar areas of the first and third layers can be reduced by forming the grounding with the second layer, which is different from the first and third layers. Since the second conductor layers are formed with the high-melting-point material, the resistance value can be made low in comparison with the device, in which conventional polycrystalline Si is used. |
