| 摘要 |
An assured monotony with increase or decrease of the combined capacitance connected to one (e.g. V1) of two reference voltages (V0,V1) is achieved by the capacitors being of the unbit type which can be connected to the reference voltages via their respective changeover switches (01-)16). The capacitors are grouped in a matrix where those in one and the same row can be selectively connected with one of two leads in a pair (e.g. L1,L2) belonging to each row. The least significant bits (b2,b1) in each digital word from a component for sampling and approximation logic (SAL) are converted to Johnson-encoded code words (j4-j1), which are used as control signals for the changeover switches (01-016). The most significant bits (b4,b3) are converted to digital words (1-s8) which are used as control signals for the changeover network used so that each of the leads (L1-L8) can be selectively connected to the reference voltages. |
