发明名称 |
Process of fabricating TiW/Si self-aligned gate for GaAs MESFETs |
摘要 |
A major difficulty with fabricating GaAs digital logic circuits using enhancement-mode MESFETs has been the large gate-source and gate-drain parasitic resistances inherent in conventional designs. A self-aligned gate process is presented, which incorporates a "mushroom" gate structure for self-aligning both an n+ implant and the source/drain contacts to the gate, thus minimizing the parasitic resistances. The "mushroom" gate consists of a two-layer TiW/Si metallization in which the bottom TiW layer is undercut with a closely controllable chemical etch. The process is compatible with the high temperature anneal necessary to activate ion-implanted GaAs.
|
申请公布号 |
US4712291(A) |
申请公布日期 |
1987.12.15 |
申请号 |
US19850741643 |
申请日期 |
1985.06.06 |
申请人 |
THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE AIR FORCE |
发明人 |
MCLEVIGE, WILLIAM V. |
分类号 |
H01L21/285;H01L21/3213;H01L21/338;(IPC1-7):H01L21/283 |
主分类号 |
H01L21/285 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|