发明名称 FACSIMILE ENCODING AND DECODING CIRCUIT
摘要 PURPOSE:To quickly encode and decode signals according to a variety of encoding systems by providing more than two processors with the same constitutions and more than two work RAMS with the same constitutions for each processor. CONSTITUTION:More than two processors 1 with the same constitutions and more than two work RAMs 2 with the same constitutions(FIFOs are used if necessary) for each processor are provided. The processor 1 is connected by one or more work RAMs 2, processes input and output, detects a changing point, refers to an encoding table and a decoding table and restores a picture. The processor operates cocurrently and independent of the other. Thus time required for encoding and decoding can be reduced roughtly to the inverse of the number of processors thereby attaining the quick processing.
申请公布号 JPS62281679(A) 申请公布日期 1987.12.07
申请号 JP19860125386 申请日期 1986.05.30
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 KANAYAMA HIDEAKI
分类号 H04N1/413 主分类号 H04N1/413
代理机构 代理人
主权项
地址