发明名称 Apparatus for arithmetic processing.
摘要 <p>In a high-speed arithmetic processor (30), a first number that has an absolute value that can exceed one is multiplied by a second number that has an absolute value not exceeding one. If the first number exceeds one it is divided into an integer and a part having a value less than one. The second number is accumulated as an addend a number of times equal to the integer to produce a sum. The second number and the part of the first number having a value less than one are supplied to a multiplier (43) to produce a partial product. An adder (45) adds the partial product to the sum, thereby obtaining a final product of the first and second numbers. The multiplication is thereby performed in a number of steps which is minimized and never varies, regardless of whether the absolute value of the first number is, for example, less than one, at least one but less than two, or at least two but less than three. This speeds up the arithmetic processing and simplifies the programming therefor.</p>
申请公布号 EP0247383(A2) 申请公布日期 1987.12.02
申请号 EP19870106323 申请日期 1987.04.30
申请人 SONY CORPORATION 发明人 HASEBE, ATSUSHI
分类号 G06F7/53;G06F7/52;G06F7/552 主分类号 G06F7/53
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