| 摘要 |
PURPOSE:To obtain a surely operating watchdog timer by inputting a reset signal to a CPU when a clock generator is stopped or the CPU ceases writing determined data. CONSTITUTION:If the output of a clock generator 1 is stopped, the CPU reset signal is outputted from a reset signal terminal 10 to stop the abnormality like runaway of the CPU because an output pulse signal A of a differentiating circuit 2 disappears and the output of an OR gate 5 disappears. If the signal is not inputted from the CPU to the D input terminal and the clock input terminal of D F/F 17 because of the abnormality of the CPU though the clock generator 1 is operated, a Q output signal B of the D F/F 17 goes to a certain level, and the output of an exclusive OR gate 18 disappears. Consequently, the second frequency divider 14 is not cleared, and respective frequency division output terminals Q1, Q2...Qn go to the high level, and a high-level signal is inputted from an inverter 16 to an OR gate 7, and the reset signal is outputted from the reset signal terminal 10.
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