| 摘要 |
PURPOSE:To obtain a high resolution DA converting circuit by sampling and outputting a pulse train of a prescribed period having a duty corresponding to a low-order M-bit in a (N+N) bit, adding the result to a high-order N-bit digital value so as to output the N-bit value and applying DA conversion to the result. CONSTITUTION:A latch circuit 101 latches a digital value 11 of (N+M) bit input by using a sampling clock 12. A pulse width control circuit 102 receives a digital value 14 of low-order N-bit in an output of the circuit 101 and outputs a specific pulse train 15 to an adder 103. The adder 103 receives the pulse train 15 and the digital value 13 of the high-order Nbit being the output of the circuit 101 and adds the both. A latch circuit 104 latches a digital value 16 being the result of addition of N bits outputted from the adder 103 by using a sampling clock 17. Further, the circuit 104 outputs an N-bit digital value 18 to an N-bit DA converter 105. The converter 105 receives the N-bit digital value 18, applies analog conversion to it and outputs an analog value 19.
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