| 摘要 |
in a digital signal processing system, a data input cycle, an arithmetic operation cycle and a data output cycle are serially arranged in each time slot. The data input cycle of the (k+1)th (k=0,1,2,3...) time slot, the arithmetic operation cycle of the (k)th time slot and the data output cycle of the (k-1)th time slot are parallelly allotted into the same duration. These cycles are executed by using a data set having a fixed data format and an instruction code which is included in the head of the data set. |
