| 摘要 |
<p>PURPOSE:To provides a simple constitution consisting of one timer circuit by adding the cycle of a timing pulse outputted from respective central processing units within a prescribed time interval and forming a set pulse when the value is larger than the relaxation of the respective prescribed time intervals of the respective central processing units. CONSTITUTION:There are provided a cycle addition circuit 13 to which the timing pulses of the plural systems outputted within the prescribed time interval are supplied, while the plural central processing units 101-10n respectively normally operate and forming the cycle addition pulse of the cycle obtained by adding the respective cycles of the timing pulses of at least plural systems and a timer circuit 17 for timing the cycle of the cycle addition pulse and forming a reset signal when the value is larger than the sum of the respective prescribed time intervals of at least plural central processing units and resetting the plural central processing units 141-14n respectively. The timing pulse outputted from plural CPUs respectively are added by the respective cycles, the added cycles are compared with the prescribed time intervals of the plural CPUs to form the reset signal. Accordingly, the timer circuit may be single.</p> |
