| 摘要 |
PURPOSE:To eliminate an execution speed from decreasing by providing plural multiplexing means and determining which memory in a couple a central processing unit and a peripheral device accesses according to a decoding result. CONSTITUTION:The central processing unit 1 can access both memories 11 and 12 and when it access, for example, the memory 11, multiplexers 3 and 5 are placed on the sides of an address bus 13 and a control bus 14 respectively, and thus the output of a two-way buffer 8 is inhibited and the output of a two-way buffer 7 is validated. At this time, while the multiplexers 4 and 6 are switched to the sides of the address bus 16 and control bus 17 respectively, the output of a two-way buffer 9 is inhibited and the output of a two-way buffer 10 is validated, so that a magnetic disk controller 2 is enabled to access the memory 12. |
