| 摘要 |
PURPOSE:To obtain a normal timing phase even if transmit data includes continuous 0s or 1s by comparing a current split phase code with a code which is one bit before it on the basis of the 1st clock signal obtained from a split phase code and also compar ing said result with the 2nd and the 3rd mutually 180 deg. out-of-phase clock signals gener ated from the 1st clock signal, counting coincidence signals by plural counters, and making a majority on their counted values and using the 2nd or the 3rd signal for decoding. CONSTITUTION:An exclusive OR circuit 23 compares the current code (a) with the code which is one bit before by the signal (b) and the output of a circuit 26 is as shown by (e). The output of an FF 22 is as shown by (f) and (g). This signal is compared by circuits 24 and 25 with the signal (e) and their coincidence signals are counted by counters 27 and 28. If there is a coincidence signal generated by the circuit 25, the counter 28 counts it and its overflow signal (j) is supplied to even a majority circuit 35. The circuit 35 inputs a signal (j) every time the output of an OR gate 29 is generated and resets an FF 30 when >=4 out of five outputs of the circuit 29 are the signal (j). Therefore, an MPX 31 inputs an A input, a signal (f) is applied to the D input terminal of an FF 33, and an FF 22 latches the output of the MPX 31 on the basis of the signal (b). An FF 34 latches a code (a) and decodes it. |
