| 摘要 |
PURPOSE:To lower the frequency of a clock circuit without any decrease in accuracy by holding an oscillation output frequency with invariably the same phase difference from printing timing. CONSTITUTION:The frequency (f) of a crystal oscillator 4 is applied as a control voltage to a voltage-controlled oscillator 3 by integrating the sum of the 1/n frequency division frequency output of a frequency divider 6 and the output (f) of a phase comparator 5 by an integration circuit,13. A trigger signal (a) when rising operates a one-shot multivibrator circuit 1, whose output (e) is inputted to the control terminal 3' of the voltage-controlled oscillator 3 while the oscillator 3 is stopped from oscillating. The time signal (e) from the rise of the trigger signal (a) to the start of oscillations is constant and the start timing of the frequency divider 6 for phase comparison is obtained from the crystal oscillator 4, so the time of phase control is constant and constant phase relation is maintained at any time. |
