| 摘要 |
PURPOSE:To increase the operating efficiency of a MOS transistor (TR) in the same chip size and to decrease the chip size by decreasing number of complementary MOS TRs by two to constitute the titled circuit. CONSTITUTION: One N-channel MS TR (MOS TR for DATA signal) is eliminated from a 2-input NAND being a gate control circuit of a P-channel MOS TR of an output inverter and the source of the remaining N-channel MOS TRs is connected to a DATA' signal. Further, one P-channel MOS TR (TR for DATA signal) is eliminated from a 2-input NOR, and the source of the remaining P-channel MOS TR is connected to a DATA' signal. When an OE signal is at a high level, a TR Q1P is turned off, a TR Q1N is turned on, and since the OE signal is at a high level, the OE' signal goes to a low level, a TR Q2P is turned on and a TR Q2N is turned off. In bringing the level of the DATA signal to the low level in this state, a TR Q3P is turned on and a TR Q3N is turned off. Since the TR Q2P is turned on, the gate potential of the TR Q4N goes to a high level, the TR Q4 is turned on and an output Y goes to a low level. |
