Circuit arrangement for reducing an interference current which is caused in a load

摘要

The invention relates to a circuit arrangement for reducing the interference current which is caused by a load (2). The frequency of the interference current is considerably higher than that of the current of a supply voltage source (1) which is coupled to the load (2). A compensation circuit is provided in order to reduce the interference current. This compensation current contains a parallel-connected series circuit which is arranged in the supply leads between the load (2) and the supply voltage source (1) and comprises a capacitor (3) and a controlled signal source (4). The signal source (4) supplies a current through the capacitor (3), which current is dependent on a control signal derived from the interference current and whose magnitude and phase are dimensioned such that the majority of the interference current can flow through the capacitor (3). <IMAGE>