Bit synchronization circuit.

摘要

A bit synchronization circuit for regenerating a synchronized clock signal synchronized with a received digital signal, comprises a phase monitoring circuit (3) for detecting bit by bit the phase progress or delay of the synchronized clock signal with respect to the digital signal to supply a phase difference signal; and a phase control circuit (14) responsive to the phase difference signal for adjusting bit by bit the phase of the synchronized clock signal so as to synchronize it with the digital signal, the phase adjustment of the phase control circuit having no transition between progress and delay adjustments.