发明名称 BLOCK ADDRESS TRANSMISSION SYSTEM
摘要 <p>PURPOSE:To reduce a transmission capacity regardless of the size of the generation probability of a block to be transimtted, and to improve transmission efficiency, by dividing an animation signal into plural number of bits on a picture plane, and transmitting the address of the block to be transmitted. CONSTITUTION:The picture plane is divided into (MxN) number of blocks, and they are sequentially scanned in a horizontal direction, and the picture data of the blocks are encoded. When a clock signal CK which represents the boundary of the block is inputted to a direct address generation circuit 4, it is counted up in order, and thc direct address DA of the block in scanning is generated. Also, an identification signal DI is represented as 'l' or '0', depending whether the block in scanning is to be transmitted or not, and is stored at a shift register 5 synchronizing with the clock signal, and also, it is supplied to an indirect address generation circuit 6. At respective stage of the shift register 5, the identification signal DI of the block adjacent to the block especially requested to be transmitted at present, is stored. A change-over switch 7 selects either the transmission mode of a direct address, or that of an indirect address, depending on whether a selection signal is 'O' or 'l'.</p>
申请公布号 JPS62227286(A) 申请公布日期 1987.10.06
申请号 JP19860072139 申请日期 1986.03.29
申请人 TOSHIBA CORP 发明人 FUJIWARA HISAO;DATAKE KENJI
分类号 H04N19/50;H04B14/00;H04N19/00 主分类号 H04N19/50
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