发明名称 CLOCK MODE SETTING ERROR DETECTION SYSTEM
摘要 <p>PURPOSE:To easily and quickly detect error by providing a phase comparison section and a phase change quantity supervisory section in a communication equipment, and using the communication equipment to detect a clock mode setting error. CONSTITUTION:The communication equipment 1 consists of an oscillator 10, a phase comparison section 11 and a phase change supervisory section 12. The oscillator 10 sends a clock ST to the phase comparator 11 and the terminal equipment. The phase comparison section 11 consists of differentiation circuits 111,112 and the comparator 113, and the phase of the clock ST is comapred with the phase of the received data SD. The phase change quantity supervisory section 12 consists of a supervisory device 121, supervises the change of the phase of the clock ST and the data SD and raises alarm when a prescribed change is exceeded. Thus, the clock mode setting error is detected quickly and easily.</p>
申请公布号 JPS62226739(A) 申请公布日期 1987.10.05
申请号 JP19860068784 申请日期 1986.03.28
申请人 FUJITSU LTD 发明人 NAKAMURA MASARU
分类号 H04L7/00;H04L25/40 主分类号 H04L7/00
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