发明名称 TESTING METHOD OF WAFER INTEGRATED CIRCUIT
摘要 PURPOSE:To test each circuit block without the effect of a circuit block, in which a power source line is shorted, by providing a power source feeding lines for test only, and feeding a power source to each circuit block independently. CONSTITUTION:On a wafer 5, individual circuit blocks 6a, 6b, 6c and 6d are mounted, and power source voltage feeding terminals 7a and 7b and grounding- potential feeding terminals 8a and 8b are formed. Power source voltages only for testing, which are different from the operating power source for a system constituted by the good individual circuit blocks among the blocks 6a-6d, are applied to the terminals 7a and 7b. The ground potential is applied to the terminal 8a and 8b. The blocks 6a-6d comprise self-testing circuits (12-15). In this way, the testing of the individual circuit blocks other than the individual circuit blocks with the fault of power source short circuits can be performed normally, without affecting the other individual circuit blocks.
申请公布号 JPS62217625(A) 申请公布日期 1987.09.25
申请号 JP19860061270 申请日期 1986.03.19
申请人 FUJITSU LTD 发明人 TSUCHIYA SHINPEI;YAMASHITA KOICHI
分类号 H01L21/66;G01R31/26;H01L21/822;H01L27/04 主分类号 H01L21/66
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