发明名称 CHIP TYPE DELAY LINE
摘要 PURPOSE:To adjust the delay time with simple constitution by providing a coil pattern to one face of an insulation board, providing an electrode almost the entire other face and providing plural interdigital patterns to part of the coil pattern. CONSTITUTION:The coil patter 11 is formed on the surface of the insulation board 10 and the electrode 12 is formed on nearly the entire rear face. The interdigital patterns 13, 13' are provided at both ends of the coil pattern 11, each tip of the pattern 13a corresponding to the teeth is connected to the pattern 13b provided to the side face of the board, the pattern 13b is prolonged to the rear face to form a connection of a pad of the printed board as a leadless chip form. After the mounting on the printed board, to obtain the optimum delay characteristic, a proper number of the patterns 13a is disconnected from the coil pattern 11 to attain the adjustment. When the width of the pattern 13a is the same as the width of the coil pattern 11, the increase in the loss due to impedance mismatching is avoided and an excellent chip delay line is obtained.
申请公布号 JPS62214710(A) 申请公布日期 1987.09.21
申请号 JP19860056877 申请日期 1986.03.17
申请人 FUJITSU LTD 发明人 SATO NORIO;KASAI YOSHIHIKO;NAGANUMA RIICHI;OGAWA HIROMITSU
分类号 H03H7/34 主分类号 H03H7/34
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