| 摘要 |
PURPOSE:To form an FIFO register with less hardware by providing a control means that activates the continuous writing of data to a data register when the number of stages including data in the data register attains a set value. CONSTITUTION:An FIFO write circuit 5 writes data with an m-bit width in a clock A from the data register 2, while an FIFO read circuit 5 reads data with an m-bit width in a clock B out of the data register 1. It is assumed that a clock C is required for the FIFO write circuit 4 to write data after an FIFO write ready signal 9 becomes active. Here a minimum integer among (x) satisfying the inequality An+C>B(n-x) is l. Data is sequentially read out of the FIFO register 1 at a constant speed, and remaining effective data in the FIFO register 1 is sequentially shifted at the read end, and the FIFO write ready signal 9 is made active at the time when l-staged effective data disappears in the write end. Then the FIFO write circuit 4 can continuously write n-pieces of data.
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