| 摘要 |
PURPOSE:To limit the time necessary for address conversion to only a gate delaying time only by corresponding a two-dimensional address space with the different ratio of the size in one direction and other direction to one- dimensional address space expressed by a constant number of the digit. CONSTITUTION:Numeric value dividing circuits 15 and 16 divide an X direction address and a Y direction address into a higher order side and a lower order side respectively. The higher order side of the X direction address and the higher order side of the direction address are inputted to a numeric value converting circuit 14, and the lower order side of the X direction address and the lower order side of the Y direction address are supplied as two bits out of 10 bits of the address of a memory circuit 2 directly. Conversion is realized by the circuits 15 and 16 and the circuit 14. The 16 bit data obtained by the circuit 14 are shifted in accordance with the value added to a shifting quantity supplying terminal 13 from the external part by a multi-digit shifter 11 of an input 16 bit and an output 8 bit, and the output 8 bit of the multi-digit shifter 11 is used as 8 bits out of 10 bits of the one-dimensional address of the memory circuit 2.
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