| 摘要 |
PURPOSE:To obtain an output signal with excellent S/N by adopting the voltage read system for a read means. CONSTITUTION:Signal input terminals S1-Sm are connected to a reset bias terminal 101 via reset analog switches SWd1-SWdm and a voltage Vbt is fed to the rest bias terminal 101. Further, the signal input terminals S1-Sm are connected to a common signal line 102 via analog switches SWt1-SWtm. Analog switches SWr1-SWrm are provided respectively to the analog switches SWt1-SWtm and each one terminal is connected in common to the reset bias terminal 101 and the other terminals are connected to a common line 103. Control terminals of bits corresponding to the analog switches SWt1-SWtm and SWr1-SWrm are connected in common to a common output terminal of gate circuits GT1-GTm. Since the system reading a voltage appearing at the common signal line 102 and the common line 103 is adopted, when a conductance gm of each analog switch has a certain value or over, the reduction in the S/N due to the variation is avoided.
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