| 摘要 |
PURPOSE:To generate a parity with a few operation steps only by executing the division based on the parity generation polynomial and the division based on the reciprocal polynomial sequentially so as to use each multiplier multiplying a constant value only and to eliminate the need for a memory storing lots of coefficients in generating the parity of the (n,k) reed solomon code where the parity exists between data. CONSTITUTION:A gate circuit 27 inputs a zero vector to allow a gate circuit 34 to pass through an input and all data selectors 291-29n-k, 321-32n-k-1, 33 are subjected to switching control so as to output selectively an input signal to the 2nd input terminal B from an output terminal Y. As a result, the results of division R1'-Rn-k' remaining in registers 301-30n-k are used as initial values and an input terminal 26 is disconnected from the entire circuit so as to constitute the division circuit using the reciprocal polynomial G*(x) using an input element of 0. Thus, a simple constitution multiplying a constant multiplication coefficient only is adopted for multipliers 311-31n-k, 35.
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