| 摘要 |
<p>PURPOSE:To attain a test carried out when a drain address circuit is used at the same impressed voltage as when it is actually used by installing an inspection memory cell in the output block of a memory cell array and setting it at a writable state at the time of inspecting drain stress. CONSTITUTION:At the time of an address input terminal A1 is set to H after normal writing is performed, column decoder outputs 1X-4X become H through an X decoder 18. A Y decoder 17 sets word lines WL1-WL4 to a potential zero to attain a drain stress state. Simultaneously an input buffer 161 controls a switch circuit 21 and supplies a write voltage Vpp to the control gate of an inspection memory cell DM. In that state, the write voltage Vpp is impressed on the drain of the cell DM through a write/nowrite switching circuit 19 in accordance with a write control signal WCS. The cell DM becomes an on state, and the drain voltages of memory cells M1, M<2>... attain the same value of a normal writing action. Accordingly the drain stress can be tested under the same conditions as actual using ones.</p> |
