| 摘要 |
PURPOSE:To inexpensively realize a quick memory switching system by providing a means issuing a memory strobe signal at a timing suitable for an access memory detected by a detection means and a means inhibiting an access to other memories. CONSTITUTION:A priority given memory area detection part 02 is comprised of an LM address latch 021 setting an address range covering all shared areas in slave memories LMs 1-3, and a comparator 022 comparing the output address of a microprocessor 01 and the contents of the LM address latch 021. If the address range lies within the shared area range in the slave memory through the comparison, a priority given memory access permission signal generator circuit 05 outputs an LMBSY signal, which is inputted to a master memory GM, closes a gate 20 and sets a selection signal SG in the master memory to '0'. The LMBSY signal conditions issued prior to the memory strobe signal (W/R) are inputted to gates 11-13 in the slave memories.
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