CLOCK SIGNAL SAFETY DEVICE

摘要

In a clock signal security arrangement three levels of master clock input signals and three levels of frame synchronisation signals are received. A respective average clock for each of the master clock and frame synchronisation is derived and is used to check the validity of the three input levels. Dependant upon the validity determination either the first or the second input clock signal is output as the master clock signal. the respective average clock is output as the frame synchronisation signal. Faults detected in either of the clock sets result in an interrupt alarm signal being forwarded to a control computer of a connected telecommunications exchange together with a data word identifying the faulty input signal.