| 摘要 |
<p>PURPOSE:To prevent an MPU (central processing unit) from being reset on the way of operation even if a power failure is restored to apply an external power, by providing a means which inhibits a reset signal to the MPU when the MPU is operated during the power failure. CONSTITUTION:If a power failure occurs, a detecting circuit 5 detects the reduction of the supply voltage to set an FF 3 and sets an MPU 3 to the stand-by mode. When a user hooks off a handset at this time for the purpose of performing data communication, the MPU 2 and the FF 3 are reset. If an external power source is restored when the MPU 2 is operated at this power failure time, the power-on reset function is operated as normal, and a signal (g) goes to '0', and an output signal (f) of an OR circuit 6 goes to '1'. However, a NAND gate 1 is set to the reset inhibiting state by the output of the FF 3, and the reset signal is not outputted to the MPU 2, and consequently, the executing operation of the MPU is not released.</p> |
