发明名称 |
PREFECCIONAMIENTO INTRODUCIDOS EN UN APARATO DE CONVERSION DE EXPLORACION ENTRELAZADA A NO ENTRELAZADA |
摘要 |
<p>A speed-up memory converts interlaced RGB input signals to double line-rate (progressive scan) form. A vertical detail signal is derived from the RGB input signals before or after speed-up and a vertical peaking signal is derived from the detail signal. During the first read operation of the speed-up memory both signals are added to the speeded-up signals to effect a preshoot of the resultant signal and during the second speed-up memory read operation only the peaking signal added to affect an overshoot of the resultant signals whereby alternate lines of the converted RGB signals exhibit enhanced vertical detail.</p> |
申请公布号 |
ES554267(D0) |
申请公布日期 |
1987.07.16 |
申请号 |
ES19670005542 |
申请日期 |
1986.04.23 |
申请人 |
RCA CORPORATION |
发明人 |
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分类号 |
H04N11/20;H04N5/44;H04N7/01;H04N9/64;(IPC1-7):H04N9/64;H04N9/77 |
主分类号 |
H04N11/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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