发明名称 DISPLAY DATA PROCESSOR
摘要 PURPOSE:To display bits of code information as much as possible at a time within a limited code display area by reading a bit of displayed code information appropriately corresponding to scans in an odd and an even fields on a display picture plane. CONSTITUTION:A start signal is inputted from a comparison circuit 9 to timers 11 and 12. The timers 11 and 12 output a high signal respectively after respective proper time lapse from that time. Assuming that an odd field scan is performed on a TV screen, O is set at a flag 7, and a gate 15 is turned on with the low signal of an output signal A from the flat 7, and only the high signal of the timer 11 is effective. Therefore, a time when an AND gate is opened is coincided with the time when the start code display of the odd field scan is finished, and the display of the bit of code information for the next even field scan is started. Also the time when the AND gate is closed in coincided with a timing when the display of the bit of code information for the even field scan is finished. Therefore, the bit of code information displayed at the even field scan can be read exactly with a correct timing.
申请公布号 JPS62149278(A) 申请公布日期 1987.07.03
申请号 JP19850294969 申请日期 1985.12.23
申请人 SHARP CORP 发明人 KAMIMURA SUSUMU;TSUJIOKA HIROSHI;HACHITSUKA YASUSHI;TOMINO TADASHI;YONEDA SHIGEO;SHINDO SHIGERU
分类号 H04N7/08;G06K7/016;H04N5/44;H04N7/081 主分类号 H04N7/08
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