发明名称 MASTER-SLAVE FLIP FLOP
摘要 <p>PURPOSE:To obtain a master-slave flip flop capable of diagnosing the fault of an LSI and is equipped with scan in/out function, by adding gates constituted of transistors to the master-slave flip flop constituted of an ECL circuit. CONSTITUTION:A gate group 13-18 are composed of transistors, etc. A D-type latch circuit 11 can fetch data SD for scan by triggering them with clocks SCK for scan at the time of tests in addition to system data D. At the time of normal operation, the system data D are triggered by system clocks -CKA and this master-slave flip flop is operated. When clock controlling signals DG are set to a logically high level at the time of a fault diagnosis, supply of the clocks -CKA to the latch circuit 11 can be interrupted and the latch circuit 11 can be triggered by clocks CKB instead of the clock -CKA.</p>
申请公布号 JPS62143513(A) 申请公布日期 1987.06.26
申请号 JP19850282863 申请日期 1985.12.18
申请人 HITACHI LTD 发明人 ITOU HIROYUKI;YAMAMOTO MASAKAZU;YAMADA TOSHIO
分类号 H03K3/037;H03K3/289;H03K3/2897 主分类号 H03K3/037
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