| 摘要 |
An inexpensive edge programmable timing signal generator for generating timing signals having complete edge programmability for accommodating incrementally adjustable variable pulse widths. The timing circuit is particularly useful in memory testing devices, where generation of a multiplicity of clock phases is required. A delay register delays an input timing signal generated by a coarse timing circuit by a predetermined amount of time, and a pair of rising and falling edge delay lines receive and delay the input and delayed timing signals by further predetermined amounts of time. The signals output from the rising and falling edge delay lines are applied to an OR gate, the output of which is applied to an EXCLUSIVE OR gate for selectively inverting the signal output from the OR gate. The circuit is inexpensive and takes up very little circuit board area.
|
