发明名称 PROGRAMMABLE CONTROLLER
摘要 PURPOSE:To perform fast processing by providing a data arraying device which inputs data to be inputted to arithmetic units constituting a parallel computing element from a process and sets them in an input data memory, and putting the arraying device and parallel computing element in independent operation. CONSTITUTION:A row counter 2 counts up in response to the fall of the output of a clock generator 1 to update a row number. Then, the contents of the corresponding row in a program memory 3 and input data of the corresponding row in the input data memory 4 are supplied to the parallel computing element 6 according to the row number. At this time, last arithmetic results outs 0-7 are stored temporarily in an OR arithmetic register 7 in response to the rise of the output of the clock generator 1 and the result is supplied as Ds 0-7 to an AND/OR computing element 6 similarly. In this case, the data arraying device 5 is so designed as to operate independently of the setting of data in the input data memory 4.
申请公布号 JPS62135903(A) 申请公布日期 1987.06.18
申请号 JP19850275981 申请日期 1985.12.10
申请人 HITACHI LTD 发明人 OKAMOTO TADASHI;AZUSAWA NOBORU
分类号 G06F9/38;G05B19/02;G05B19/05 主分类号 G06F9/38
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