| 摘要 |
PURPOSE:To increase the through-rate by connecting a gate of two MISFETs at the output stage to a drain of a common gate MISFET and connecting a frequency compensation circuit between an output terminal and a differential output terminal so as to prevent the increase in power consumption and the deterioration in power noise elimination ratio. CONSTITUTION:When a leading step input is impressed in the voltage follower state, a voltage at a node 6 is decreased and the drain voltage of a MISFET M6 is decreased to cut off a MISFET M14. However, the output stage of this circuit is of push-pull form and when a voltage at the node 6 is decreased, the drain voltage of the FET M8 is lowered and the absolute value of the gate-source voltage of the FET M15 of the output stage is increased. Thus, a current charged in a load capacitance CL is increased rapidly to increase the through-rate. When a trailing step input is impressed, since the source-gate voltage of the FET M14 is increased, the load capacitance CL is discharged rapidly and the output voltage is dropped rapidly, then the through-rate is also large.
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