发明名称 INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To prevent confusion on a design by a change into multilayers, and to conduct a hierarchization design using multilayer interconnections easily by each making specific wiring layers correspond to a plurality of design hierarchies in an integrated circuit having multilayer interconnection structure. CONSTITUTION:A large scale integrated circuit has wiring layers consisting of N layers, and the wiring layers are used as a first layer, a second layer ... an N-th layer toward an upper layer from a lower layer. On the other hand, a circuit in a chip is constituted of M-th order hierarchies composed of a chip level LSI circuit, etc. consisting of the interconnections of (1) fixed-shape connections among a small number of elements or in elements, (2) a simple circuit employing said (1) as a unit, (3) a circuit using said (2) as a unit and having a scale larger than 2, ... M a large scale circuit block employing said M-1 as a unit. In such a case, wiring layers for the whole layers or one part of a first layer - an n1-th layer are made to correspond to a first-order hierarchy, wiring layers for the whole layers or one part of an n1'-th layer - an n2-th layer are made to correspond to a second-order hierarchy, and wiring layers for the whole layers or one part of an nm-1'-th layer - an nm-th layer are made similarly to correspond to the connections of a chip level in an M-th order hierarchy, an uppermost layer, and circuits are connected at each hierarchy level.
申请公布号 JPS62115740(A) 申请公布日期 1987.05.27
申请号 JP19850254667 申请日期 1985.11.15
申请人 NEC CORP 发明人 ITO SOICHI
分类号 H01L21/3205;H01L21/82;H01L23/52 主分类号 H01L21/3205
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