| 摘要 |
PURPOSE:To allow all cases to receive a clock signal and a frame pulse signal of the same phase by giving an optional delay to the clock signal and the frame pulse signal and compensating the transmission delay changed depending on the length of a clock supply cable between the clock distributor and each case. CONSTITUTION:The clock distributors A1-An are installed corresponding to the clock supply cable and a switch SW 8 is set depending on the length of the cable. Three selectors 3, 6, 7 are controlled by the setting value of the switch SW 8. Flip-flop circuits 4a, 4c use a positive clock signal as a clock and flip-flop circuits 4b, 4d are driven by an inverting clock signal generated by an inverter. Thus, the frame, pulse signal outputted from the flip-flop circuits 4a-4d is delayed by a half clock each sequentially from the frame pulse signal given from the 1st selector 3. |
