| 摘要 |
PURPOSE:To decrease the number of signal lines by requesting data reading/ writing between a memory using circuit and a memory control circuit while classifying according to the size of length of on time of one signal line. CONSTITUTION:A read/write common control circuit 5 in a memory using circuit (ADP) 1 turns on a memory using signal MRQ 1 for a prescribed one machine cycle (m) time at the time of the data reading request and turns it on for two machine cycles (m) time at the time of the data writing request. A memory control circuit 6 sends a busy displaying signal BUSY 1 to an ADP 2 by the MRQ 1, simultaneously, the reading/writing request is judged by the on time of the MRQ 1 and a memory (RAM) 4 is accessed. Thus, the data reading/ writing request can be executed by one signal line and the signal line can be decreased.
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