发明名称 INTEGRATED CIRCUIT
摘要 PURPOSE:To reduce an area occupied by a check pattern, and to improve the yield of a wafer by using an L shape or a cross as the polishing check pattern employed in the polishing process of a single crystal surface on the preparation of a substrate for an integrated circuit having dielectric isolating construction. CONSTITUTION:A polishing surface appears as shown in a dotted line on an L shaped or crossed polishing check pattern by polishing a polishing range 4 in the polishing process of a single crystal surface. Accordingly, polishing size checking L1-L4 of the waveforms of the dotted line can be monitored.
申请公布号 JPS62101031(A) 申请公布日期 1987.05.11
申请号 JP19850242031 申请日期 1985.10.28
申请人 NEC CORP 发明人 NAKANO FUMIHISA
分类号 H01L21/304;B25H7/00 主分类号 H01L21/304
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