| 摘要 |
PURPOSE:To attain continuous delay with ease of change in dely amount by reading a data stored sequentially step by step at the part point of time into a memory out thereof step by step according to the sequence of its storage. CONSTITUTION:An address counter 12 consisting of a down-counter counts a clock signal CLK and gives and address signal ADD to an address multiplexer 13 as the 1st input. A set output DS of a delay amount setting circuit 15 is fetched in the timing of the clock signal CLK, a delay amount input signal DIR is given to an adder circuit 16, added with the address signal ADD and given to the multiplexer 13 as the 2nd input. A data is written by the address signal ADD at the first half period of the period of the clock signal CLK and the data is read by a summing signal SUM at the latter half period. An optional delay time is realized by changing the delay setting value. |
