| 摘要 |
PURPOSE:To obtain the titled generator with less number of elements and ease of pulse width change by giving a sinusoidal wave input to a CMOS inverter biased higher than a threshold value and to a CMOS inverter biased lower than the threshold value. CONSTITUTION:A bias higher than the threshold value is given to the CMOS inverter 5 by a bias setting circuit 3 and a bias lower than the threshold value is given to the CMOS inverter 6 by a bias setting circuit 4. In inputting a sinusoidal wave signal thetaIN via a capacitor 2, the level of the inverter 5 goes to an L level only at a part of the positive level of the sinusoidal wave and the level of the inverter 6 goes to an H level only at a part of the negative portion of the sinusoidal wave. A non-overlap biphase clock is obtained from an output, the inverse of theta1 of the inverter 5 and an output theta2 of the inverter 6. Thus, less number of elements is attained and the pulse width of the clock and the non-overlap period are changed easily by adjusting the bias voltage. |
