| 摘要 |
PURPOSE:To decrease number of memory cell MOS transistors (TRs), by connecting a data storage flip-flop to a data line via a transfer gate MOS TR, regardless of a high and a low level signal. CONSTITUTION:An inverter in which an MOS TRQ1 is connected to a high resistance element R1 and an inverter in which an MOS TRQ2 is connected to a high resistance element R2, are cross-coupled to constitute a flip-flop FF for data storage and connected between a power supply VCC and ground level. A transfer gate MOS TRQ0 for data write/readout is connected to this FF and another end of the TRQ0 is connected to a data line, where write data and readout data from the FF are given, and the gate is connected with a word line for the selection of a cell. |
