发明名称 |
Logic signal multiplier circuit |
摘要 |
There is disclosed a logic signal multiplier circuit which includes the interconnection of a plurality of inverters having outputs interconnected by a capacitor. Each of the inverters includes complementary transistors having their gates connected to a common terminal such that each inverter may be controlled by a separate clock control signal. The control signals are coupled to provide a three-phase operation of the circuit which insures (1) charging of the capacitor between the outputs of the inverters during a first time period, (2) an increase of the voltage at a node of one of the inverters to a value which is twice the value of the supply voltage driving the inverters during a second time period, and (3) coupling of that same node to ground during a third time period. Diodes are interconnected in each of the inverter circuits to prevent discharge of the capacitor during times that selected ones of the transistors forming the inverter circuits are conductive.
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申请公布号 |
US4656574(A) |
申请公布日期 |
1987.04.07 |
申请号 |
US19840651335 |
申请日期 |
1984.09.17 |
申请人 |
CENTRE ELECTRONIQUE HORLOGER |
发明人 |
SALCHLI, FRANCOIS H. |
分类号 |
H03K19/096;G04G19/00;H03K5/02;H03K19/0185;H04R25/00;(IPC1-7):H02M7/25 |
主分类号 |
H03K19/096 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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