发明名称 Method of manufacturing a semiconductor device including forming a multi-level interconnection layer.
摘要 <p>A method of manufacturing a semiconductor device comprising the steps of preparing a semiconductor substrate (31) on which a first insulation film (30) is formed, forming a first conductive layer (35) on the first insulation film (30), forming a hillock (36) on the first conductive layer (35), forming a second insulation film (35,38) on the structure, removing that portion of the second insulation film (37, 38), in self-align with the hillock (36), which is on the hillock (36), thereby forming a contact hole leading to the first conductive layer (35), and forming on the structure a second conductive layer (41) extending into the contact hole and contacting the first conductive layer (35).</p>
申请公布号 EP0216017(A2) 申请公布日期 1987.04.01
申请号 EP19860107736 申请日期 1986.06.06
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 MASE, YASUKAZU PATENT DIVISION K.K. TOSHIBA;ABE, MASAHIRO PATENT DIVISION K.K. TOSHIBA;AOYAMA, MASAHARU PATENT DIVISION K.K. TOSHIBA
分类号 H01L23/522;H01L21/3205;H01L21/768;H01L27/00 主分类号 H01L23/522
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