发明名称 CLOCK ASYNCHRONIZING DATA DETECTION SYSTEM
摘要 PURPOSE:To improve the utilizing efficiency of a transmission line by identifying a reception signal by an asynchronizing pulse string being n-times of the clock frequency, separating the string into n-set of pulse series and using the pulse series having the least error as a reception output. CONSTITUTION:The oscillating frequency of the oscillator CLK is oscillated at a frequency nearly equal to n-times of the clock frequency of a reception signal and a gate pulse subject to 1/n frequency division and having different phases is fed to a gate circuit GAT by an n-bit counter nCOUNT and a pulse distribution circuit PH, the gate circuit GAt outputs a pulse series nearly equal to the clock frequency. The output of the gate circuits GAT1, GAT2,..., GATn-1, GATn is fed to error detection circuit ERR.DET. The error detection circuit ERR.DET detects the frame signal pattern at each gate circuit GAT output, the series, having the least error number in the frame signal pattern and the series with the least error is sent as the receiver output.
申请公布号 JPS6265536(A) 申请公布日期 1987.03.24
申请号 JP19850203455 申请日期 1985.09.17
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 NAKAJIMA SHIGEO;SAKAI TSUTOMU;INOUE YUKIO
分类号 H04L25/40;H04L7/02;H04L7/08;H04L7/10 主分类号 H04L25/40
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