发明名称 PAIR RUN ENCODING SYSTEM
摘要 PURPOSE:To improve coding efficiency and to perform linear coding by selecting a pair of runs on adjacent black and white lines of a binary signal in combination, and coding the sum length of the pair of black and white runs and the length of either black or white run in each pair. CONSTITUTION:A facsimile signal from an input terminal 1 is stored in a memory 10 temporarily, and then applied to gate circuits 21-24 together with a signal delayed by one bit through a delay circuit 31. By the outputs of the circuits 21 and 22, a counter 41 counts white runs, and by the outputs of the circuits 23 and 24, a counter 42 counts black runs. The outputs of those counters 41 and 42 are added together by an adder 50 to find the run length of pairs of black and white runs. The value of this adder 50 is coded by a coder 61, whose output is applied to a signal synthesizing circuit 70; and a coder 62 references the counted value of the counter 42 to code the output of the adder 50, thereby applying the result to the circuit 70. Further, a block 2 processes white run at a large blank part on the right-hand side, and the result is applied to the circuit 70 through a coder 63, thus improving coding efficiency.
申请公布号 JPS5836073(A) 申请公布日期 1983.03.02
申请号 JP19810133281 申请日期 1981.08.27
申请人 KOKUSAI DENSHIN DENWA KK 发明人 YAMAZAKI YASUHIRO
分类号 H04N1/419;H04N1/41 主分类号 H04N1/419
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