发明名称 SIGNAL PROCESSING MULTIPLIER
摘要 PURPOSE:To calculate a variation range of the input signals with high accuracy and with no fear of overflow even with the signals out of said variation range, by providing a barrel shifter, an overflow detector and an overflow corrector to a multiplying circuit having its variation range of input signals fixed between -1 and +1. CONSTITUTION:A multiplier 5 delivers the value of (2N-1) bits as a product and a barrel shifter 6 shifts the output of a multiplier 5 in the upper direction by an amount equivalent to the value (K+L) given from an input terminal 7 for shift amount. Then the shifter 6 delivers N bits between the (K+L+1)-th bit and the (K+L+N+1)-th bit of the input given to the shifter 6. An overflow detector 10 checks the upper (K+L+1) bits of the output of the multiplier 5 and decides the generation of an overflow when all bits have no equal value. Therefore an instruction is given to a selection circuit 11 so that the negative maximum value given from an input terminal 9 for negative maximum value with the highest bit of the multiplier 5 set at '1' and that the positive maximum value given from an input terminal 8 for positive maximum value is delivered through an output terminal 12 when said highest bit is set at '0', respectively.
申请公布号 JPS6255727(A) 申请公布日期 1987.03.11
申请号 JP19850195256 申请日期 1985.09.03
申请人 NEC CORP 发明人 NISHITANI TAKAO
分类号 G06F7/38;G06F7/52;G06F7/523;G06F7/53 主分类号 G06F7/38
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